An integrated circuit device for processing a camera signal is fed with an analog signal from an image sensor or the like incorporated into a system, performs signal processing on the signal to generate a digital image signal, and outputs the signal to an image display unit incorporated into the system or an external monitor.
To be specific, an integrated circuit device for processing a camera signal is first fed with an analog signal from an image sensor or the like of the previous stage, performs signal processing on the signal in an analog processing circuit such as an analog front end (AFE) or the like to convert the signal to a digital signal, and then performs signal processing on the digital signal in a logic circuit to generate a video signal, a synchronizing signal, and so on. Thereafter, the integrated circuit device digitally outputs the signals to the image display unit or the like of the following stage in parallel together with an internal reference clock having been used in the logic circuit.
In order to easily design the timing of capturing data in the circuit of the following stage, the integrated circuit device for processing a camera signal has a mechanism for adjusting the phase of the internal reference clock to be outputted to the outside and the phases of signals including the video signal and the synchronizing signal, which are outputted to the outside, to regulate timing of output.
FIG. 7 is a schematic structural diagram showing a part of a conventional integrated circuit device for processing a camera signal. FIG. 8 is a timing chart for explaining the operations of the conventional integrated circuit device for processing a camera signal.
In the conventional integrated circuit device, after signal processing is performed on an analog signal from the image sensor or the like to convert the signal to a digital signal, signal processing is performed on the digitized signal in a logic circuit 200, desired data (digital signals) such as the video signal and the synchronizing signal is generated, and the data is outputted to the data terminals of the flip-flop circuits of a flip-flop circuit group 204. As shown in FIG. 8, the timing of internal data 202 including the video signal and the synchronizing signal is synchronized with the rising edge of an internal reference clock 201.
The logic circuit 200 is a synchronous circuit. The internal reference clock used in the logic circuit 200 is outputted to an inverter 203 and the clock terminals of the flip-flop circuits of the flip-flop circuit group 204.
The internal reference clock 201 having been inputted to the inverter 203 is inverted in phase and outputted to a clock output terminal 207 as an external output clock. The internal data having been inputted to the flip-flop circuits of the flip-flop circuit group 204 is outputted as external output data to the data output terminals of a data output terminal group 208 in synchronization with the rising edge of the internal reference clock. Therefore, as shown in FIG. 8, the timing of external output data 206 and the timing of an external output clock 205 are in opposite phase.
As described above, in the conventional integrated circuit device for processing a camera signal, the phase of the external output clock outputted in parallel and the phases of the external output data including the video signal and the synchronizing signal are adjusted by using the inverter and the flip-flop circuits to regulate the timing of output.
However, in the conventional integrated circuit device for processing a camera signal, delay caused by the influence of an internal layout (elements placed between the logic circuit and the output terminals and the wire lengths of the elements) and an external load has not been taken into consideration. For this reason, as shown in FIG. 8, the external output clock 205 and the external output data 206 are delayed and a phase difference occurs between the external output clock 205 and the external output data 206 and the internal reference clock 201 and the internal data 202, so that an area of digital noise increases and picture quality degrades. The following will describe this conventional problem.
First, regarding fluctuations of the power of the integrated circuit device, since the logic circuit operates in synchronization with the internal reference clock, as shown in FIG. 8, a power fluctuation area 209 of the logic circuit is distributed from the rising edge of the internal reference clock. On the other hand, fluctuations of the power of the output terminal depend upon a change point of the external output data and a change point of the external output clock. When a phase difference occurs between the internal reference clock and the external output clock and between the internal data and the external output data, as shown in FIG. 8, a power fluctuation area 210 of the output terminal is displaced from the power fluctuation area 209 of the logic circuit 209.
In the integrated circuit device, much digital noise occurs when the processing of the digital signal changes. When the processing is not performed or the processing of the digital signal does not change, digital noise does not occur. Thus the area of digital noise of the integrated circuit device is distributed in an area where one of the power fluctuation area of the logic circuit and the power fluctuation area of the output terminal is present. Therefore the area of digital noise is distributed as shown in FIG. 8. In the presence of a phase difference between the internal reference clock and the external output clock and between the internal data and the external output data, the area of digital noise increases. On the other hand, an area having less digital noise is distributed in an area where neither of the power fluctuation areas of the logic circuit and output terminal is present. Hence, in the presence of a phase difference between the internal reference clock and the external output clock and between the internal data and the external output data, an area 212 having less digital noise is reduced as shown in FIG. 8.
Further, the area having less digital noise varies with the operating frequency of the integrated circuit device. The area increases at a slow operating frequency and decreases as the operating frequency increases.
In a camera system, such digital noise acts as a noise source to an analog signal in an image sensor and an analog processing circuit, so that an S/N ratio decreases and picture quality degrades. Particularly in recent years, the range of uses of cameras has expanded to cellular phones and so on. Camera systems used for cellular phones have had a larger number of pixels, have been miniaturized, and have had faster operating frequencies, so that an area having less digital noise decreases and picture quality degraded by digital noise.
FIG. 9 shows propagation of digital noise in a camera system.
As shown in FIG. 9, digital noise occurring in a logic circuit 215 propagates to an image sensor 213 and an AFE 214. Moreover, digital noise occurring in an output terminal group 216 similarly propagates to the image sensor 213 and the AFE 214. As described above, in this camera system, digital noise propagates through two systems. In the presence of a phase difference between the internal reference clock and the external output clock and between the internal data and the external output data, a stable area having less digital noise decreases which allows the image sensor 213 and the AFE 214 to stably operate without being affected by digital noise.
In order to minimize the influence of digital noise, it is necessary to perform analog processing in a stable area, that is, an area where the power fluctuations of the logic circuit 212 and an output terminal 216 are minimized. However, as the operating frequency becomes faster, the stable area having less digital noise decreases and it becomes difficult to adjust the timing of analog processing to stably acquire the best picture quality.
A conventional technique for reducing the influence of digital noise is proposed, in which power fluctuations are averaged out by shifting a phase between the bits of parallel output and thus the influence of noise is reduced (For example, Japanese Patent Laid-Open No. 11-7349 (FIG. 1)).
However, when shifting the timing of outputting (phase) an external output clock and external output data including a video signal, it becomes difficult in the processing of the following stage to design the timing of receiving data by using the external output clock from an integrated circuit device. Further, the best picture quality cannot be achieved, though the influence of digital noise can be reduced. The optimum S/N ratio can be obtained when analog processing is performed in a stable area with minimum power fluctuations and the influence of digital noise is minimized.